Module Architecture

To restrain the cells at the top, I proposed a design which used the voltage sensing PCB itself as a structural plate. This board, which I designed in CAD in collaboration with the EECS team, sits directly on top of the cell array. It has precision-cut holes that fit around each cell and thick copper pads on its surface that the wirebonding machine bonds directly to, making the cell-to-cell electrical connections. Because it spans the full footprint of the module and is fastened to the structure on its short edges, it also acts as the plate that keeps the cells from moving upward under load. One part doing two jobs, drastically lowering our part count, and simplifying our manufacturing efforts substantially. This change removed multiple machining operations on the cell restraints that would have been necessary otherwise.

The wirebonding process is worth explaining briefly because it is what makes this module design possible. Instead of spot-welding tabs between cells like many custom battery packs, ultrasonic wirebonding uses a CNC mahcine to draw a thin copper wire across the surface of each cell terminal and bonds it in place using high-frequency vibration. Each wire is thin enough to act as its own fuse, called a fusible link. If a cell fails and draws too much current, its fusible inks melt open and isolate it from the rest of the pack. The beauty of this approach is that the high precision connections allow both the positive and negative connections to be made on one surface of the battery cell. The positive bond is made directly to the terminal on the top of the cell. The negative bond is made to the rim of the cell, where the heat shrink has been trimmed back a few mm to expose the negative rim of the can. This leaves the bottom surface of the cell completely free, where we monitor cell temperatures.

Analysis

The VSense PCB structural analysis was the most involved FEA I ran on this project. Because FR4 is a layered composite material, I used anisotropic FEA techniques to model it in SolidWorks, which required manual material design in the software. The failure mode, cracking or cells coming loose inside a live high-voltage pack, was serious, as reflected by FSAE’s requirement that cell restraining parts must be able to withstand an acceleration of 40g in every direction. To ensure our novel approach to cell restraint would be compliant, I ran these FEAs many times on variable PCB thicknesses to determine preciesly what spec of material was necessary to keep both deflection and factor of safety within our tolerances. That analysis drove the selection of 3mm as our PCB thickness. I repeated this FEA a few times as other parts of the assembly became finalized, including the full screw pattern and all structural components, confirming the assembly as a whole stays well below yield.

Because we use wirebonds as fusible links for per-cell overcurrent protection, FSAE rule EV.6.6.5 requires that they be formally rated, either with manufacturer data or with test data we generate ourselves. No data existed for our specific wire dimensions and bond parameters, so I designed a rule compliant testing program to collect it. The setup passes variable high current through individual fusible links using a high-power low-voltage source to hit target current levels. To measure current and fuse time through links of varying wire diameter, bond length, and material, voltage across a shunt resistor is sampled at over 200 Hz to capture the full current waveform and time to fuse. FSAE requires a minimum of four trials at each of at least four current levels for the data to qualify. I documented the full experiment design, instrumentation requirements, safety protocols, test fixture design, and data recording procedure in a detailed DOE and SOP so that team members could execute the testing independently. The team is currently running those tests.

FSAE rules require thermistors to be in direct contact with the cell they are monitoring, or to demonstrate equivalent thermal coupling through whatever interface material separates them. This posed a problem for our design: the thermistors are on a low-voltage PCB, so they need to be electrically isolated from the cells, which are live high-voltage surfaces. Placing an insulating material between the thermistor and the cell was necessary for safety, but we had to prove that material would not meaningfully slow the thermistor’s thermal response. I ran a 1D transient heat conduction simulation in MATLAB, modeling a step change in cell surface temperature and solving for the temperature at the thermistor over time across different material thicknesses and thermal conductivities. These simulations were the basis for selecting a specific thermal gap filler interface material that met all four of our constraints simultaneously: thermal conductivity fast enough to satisfy the FSAE direct-contact equivalency requirement, sufficient dielectric strength to electrically isolate the PCB from the cells, and physical properties compatible with our fabrication and assembly process.